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alexislms's avatar
alexislms
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1 year ago

Constraint file for async_fifo macro?

Where is the constraint file for the async_fifo macro in quartus 23.4?

I get a bunch of CDC timing... why isn't it loaded by default with the module?

Timing

3 Replies

  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    Icon for Contributor rankContributor
    1 year ago

    To figure out your question, you are using fifo ip to perform asyn fifo function but there are timing violations in timing analyzer right?

    If so can you share your project archived, you can remove your RTL file but please make sure the timing path can be showed in timing analyzer thanks.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Not sure if you have update on the above? We will need your design to investigate on this.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.