Forum Discussion
ContributorConstraint clocks of SPI interfa
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
Super ContributorSo you are clocking the external device with an output clock, basically source synchronous. You need a generated clock constraint targeted to the output and the output port for that clock should have a false path constraint so it is not being analyzed as a data output. You should not perform a data analysis on a clock output. So for example:
#not sure why this was commented out and incomplete unless you were trying to create a virtual clock and is it SCLK1 or SCLK2 out?
create_generated_clock -name {sclk1_clk} -source [get_pins pll_inst|clk[0]] [get_ports {SCLK1}] -divide_by 1
set_false_path -to [get_ports {SCLK1}]
#-reference_pin was incorrect here; delay values could simply be Tsu for max and -Th for min if clock and data traces on board are matched delay
set_output_delay -clock sclk1_clk -max 5 [get_ports {MOSI1}]
set_output_delay -clock sclk1_clk -min -5 [get_ports {MOSI1}]
anonimcsHi @sstrell ,
This way I do not get any setup/hold time violations but I am still not fully convinced if this is the way to go. When I report clocks / clock tree, I do not see the virtual clocks "pll_clk" (yes, I uncommented those lines) and "sclk1_clk" in any of those reports. In addition, I do see that the 'create_generated_clock' commands for these two virtual clocks are also reported to be ignored constraints in the Timing Analyzer. Same goes for the miso1/mosi1 constraints, I can see them under Ignored Constraints as well. So what I did in my .sdc file is as follows:
#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clk} -period 100MHz [get_ports {clk}] create_clock -name altera_reserved_tck -period 24.000MHz [get_ports altera_reserved_tck] #************************************************************** # Generated clocks #************************************************************** derive_pll_clocks derive_clock_uncertainty # Specify generated clock from PLL (PLL output is 100MHz) set_instance_assignment -name corepll_inst|altpll_component|auto_generated|pll1 -to pll_inst create_generated_clock -name {pll_clk} -source [get_pins pll_inst|inclk0] [get_pins pll_inst|clk0] -divide_by 1 # create SPI clocks of 50MHz create_generated_clock -name {sclk1_clk} -source [get_pins pll_inst|clk[0]] [get_ports {SCLK1}] -divide_by 2 set_false_path -from * -to [get_ports {SCLK1}] set_input_delay -clock {sclk1_clk} -max 4 [get_ports {MISO1}] set_input_delay -clock {sclk1_clk} -min 2 [get_ports {MISO1}] set_output_delay -clock {sclk1_clk} -max 5 [get_ports {MOSI1}] set_output_delay -clock {sclk1_clk} -min -5 [get_ports {MOSI1}]I don't know if that makes any difference here but I'm using Quartus Standard Version 21.1. Not sure what I'm missing here in the sdc...
