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maitreya_ranade
New Contributor
New ContributorConstraining SPI flash lines
I am trying to constrain Flash SPI lines. These are my specifications: FPGA Clock: 100MHz (Derived from PLL) SPI Clock: 50Mhz SPI Master: FPGA SPI Clock generation: FPGA The FPGA is using the...
KennyT_altera
Super Contributor
Super ContributorNot sure if you have further question for the above? If no, we shall close this thread.
