Constraining LEDs/Switches to VHDL onDE1-SoC

I was able to constrain the VHDL clk, but now the tool says clk_div is unconstrained which I do not understand because it is just a clock generated based on the count of a register that is iterated by the tick of clk. Do I have to write a constraint in the sdc for this clock as well?

https://alteraforum.com/forum/attachment.php?attachmentid=15323&stc=1

in de1soc_master.qsf

set_global_assignment -name FAMILY "Cyclone V"

set_global_assignment -name DEVICE 5CSEMA5F31C6

set_global_assignment -name TOP_LEVEL_ENTITY "DE1_SoC"

set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name clk_gen.sdc# set_global_assignment -name SDC_FILE DE1_SoC.sdc

new constraint clk_gen.sdc

create_clock -period 20 [get_ports clk]