Forum Discussion
Altera_Forum
Honored Contributor
7 years agoIt is clearly a problem with the constraints
https://www.alteraforum.com/forum/attachment.php?attachmentid=15316 https://www.alteraforum.com/forum/attachment.php?attachmentid=15317 It is clear my qsf is reading the sdc because if I mess with the .sdc, it will fail to compile. I am not sure how to create and connect my VHDL clk input to a real clk Here are the critical warnings I am seeing https://www.alteraforum.com/forum/attachment.php?attachmentid=15318