constant expression cannot contain a hierarchical identifier

Hi people,

I'm very new to SystemVerilog, and learning how to write synthesizable code right now. Could you help me with an issue?

Please take a look at the code:

typedef struct{
  int a;
  int b;
  int c;
} params_t;
module A (clk, rst, out);
  
  parameter params_t params = '{2, 3, 4};
  
  input logic clk, rst;
  output logic  out;  //line 12!
  
  always @ (posedge clk, posedge rst) begin
    if(rst == 1'b1) begin 
      out <= '0;
    end else begin
      out <= out + params.b;
    end      
  end
    
endmodule

Quartus II (9.1) gives an error at the line 12:

"constant expression cannot contain a hierarchical identifier"

The problem seems to be that I want to use parameters defined in a structure to make the design more generic. With VHDL it works fine. Am I allowed to do it in SV, or is it just Quartus issue? It would work if I would use the parameters without putting them into a structure, but it's ugly. How would you do it on my place?