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Altera_Forum's avatar
Altera_Forum
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8 years ago

consept to create a smaller clock (example) and synchronized data

Hi, I do not understand to complete the concept of using the 50mhz in other cases, sometimes I need a specific clock, and I do not understand this.

I see tutorials that create the divider clock with different phrases, but I do not understand which is the clearest idea, I confused: some use "wait for us" others using sentences "yes" and rising_edge or check change Whit "Variable'event" No I know if I use arithmetic to divide and multiply the 50mhz signal.

in others cases i need other clock for synchronized bits in 9600bps in UART, but i not finished this work, Now I tried to create a clock for ADC in the range of .8mhz to 3.2mhz for the use of this adc

Do you explain a simple idea and simple code for this in VHDL? The various tutorials have confused me.

thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Okay, let's go through your points one by one. But first, I make the assumption that you're using an FPGA eval board, since you're mentioning "the 50 MHz".

    First, there's "wait for ... us". You only need this for simulating your code. You can use this to simulate a clock source. However, you cannot synthesize this and load it to your FPGA.

    Then there's "others using sentences "yes""; I don't understand.

    Next, "rising_edge or check change whit "variable'event"". That's just your standard synchronous process. You should understand those first before going to more complex topics like building your own clock divider and UART, but I presume you already do and just got confused. Well, you can use this to build a clock divider: 

    
entity xyz is
  clk: in std_logic;
-- ...
signal divided_clk: std_logic := '0';
-- ...
process(clk) is
begin
  if(rising_edge(clk)) then
    divided_clk <= not divided_clk;
  end if;
end process;

    Now you can use "divided_clk" as a clock for another process, and it'll run at half the clock rate!

    However, that has its own disadvantages. My recommendation: assuming you're using an FPGA, it'll have a PLL. A PLL is basically a component that receives a clock (your 50 MHz) and generates another clock from it (e.g. 10 MHz). Just search for "ALTPLL".

    So, in short, my recommendation for your particular problem:

    [LIST=1]

    [/LIST]

    • Make sure you understand how to develop synchronous logic

    • Make sure you understand how to instantiate entities

    • Use Quartus to generate an ALTPLL block that generates the clock you need

    • Wire the ALTPLL instance to your design