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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
Solved

Connection bit order between hierarchy

Hi, I got unintended bit order of bus connection between SystemVerilog top with Block Design in lower hierarchy. I intend to connect inst3 to out[3] but Quartus connected in reversed order. Please...
Compilation
  • ZiYingE_Altera's avatar
    ZiYingE_Altera
    2 months ago

    Hi Masaru,
     

    Thank you for the clarification. 
     

    After confirming once again with the Altera design team using the original design along with the information from the additional forum link that have been provided, this issue has been identified as a known software bug. As BDF has been deprecated and is no longer supported in newer Quartus releases, no fix is planned for this issue.

    Here are some of the suggested workaround you may work with: 

    1. Avoid using .bdf files by converting them to Verilog or VHDL in Quartus Prime Standard Edition using File → Create/Update → Create HDL Design File from Current File, and then use the generated HDL files in Quartus Prime Pro.

    2. Replace the SystemVerilog top-level module with a VHDL, AHDL, or BDF top-level design to avoid the bus-ordering issue.

    3. Continue using your existing workaround with the streaming operator (<<) to resolve the bus ordering.

     

    We understand this may not be the outcome you were hoping for, and we apologize for the inconvenience. Please feel free to reach out if you have any further questions or concerns. If there are no further questions or updates, we may proceed with closing the support ticket accordingly.
     

    Best regards,
    ZiYingE_Altera

ZiYingE_Altera's avatar
ZiYingE_Altera
Icon for Contributor rankContributor
2 months ago

Hi Masaru,
 

Thank you for the clarification. 
 

After confirming once again with the Altera design team using the original design along with the information from the additional forum link that have been provided, this issue has been identified as a known software bug. As BDF has been deprecated and is no longer supported in newer Quartus releases, no fix is planned for this issue.

Here are some of the suggested workaround you may work with: 

1. Avoid using .bdf files by converting them to Verilog or VHDL in Quartus Prime Standard Edition using File → Create/Update → Create HDL Design File from Current File, and then use the generated HDL files in Quartus Prime Pro.

2. Replace the SystemVerilog top-level module with a VHDL, AHDL, or BDF top-level design to avoid the bus-ordering issue.

3. Continue using your existing workaround with the streaming operator (<<) to resolve the bus ordering.

 

We understand this may not be the outcome you were hoping for, and we apologize for the inconvenience. Please feel free to reach out if you have any further questions or concerns. If there are no further questions or updates, we may proceed with closing the support ticket accordingly.
 

Best regards,
ZiYingE_Altera

MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Hi Zi Ying,

Ok, I am happy with your workarounds.

I agree with closing this ticket.

Thank you for your help.

Masaru

  • ZiYingE_Altera's avatar
    ZiYingE_Altera
    Icon for Contributor rankContributor
    2 months ago

    Hi Masaru,

    Thank you for the update and for taking the time to work with us. I will proceed with closing this ticket. However, we will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    ZiYingE_Altera