Forum Discussion
Occasional ContributorConnection bit order between hierarchy
Hi Masaru,
Thank you for the clarification.
After confirming once again with the Altera design team using the original design along with the information from the additional forum link that have been provided, this issue has been identified as a known software bug. As BDF has been deprecated and is no longer supported in newer Quartus releases, no fix is planned for this issue.
Here are some of the suggested workaround you may work with:1. Avoid using .bdf files by converting them to Verilog or VHDL in Quartus Prime Standard Edition using File → Create/Update → Create HDL Design File from Current File, and then use the generated HDL files in Quartus Prime Pro.
2. Replace the SystemVerilog top-level module with a VHDL, AHDL, or BDF top-level design to avoid the bus-ordering issue.
3. Continue using your existing workaround with the streaming operator (<<) to resolve the bus ordering.
We understand this may not be the outcome you were hoping for, and we apologize for the inconvenience. Please feel free to reach out if you have any further questions or concerns. If there are no further questions or updates, we may proceed with closing the support ticket accordingly.
Best regards,
ZiYingE_Altera
ContributorHi Masaru,
Thank you for your patience.
The issue you are seeing is related to a bug in Quartus Prime Pro during the elaboration of a System Verilog module that instantiates a BDF module. However, since BDF support has been deprecated in Quartus Prime Pro Edition starting from version 23.3, this issue is not planned to be fixed.
As a workaround, you may:
- Convert all BDF files to Verilog or VHDL
You can use Quartus Prime Standard Edition to perform the conversion:
- Create and open a Quartus project.
- Open the target BDF file.
- Select File → Create/Update → Create HDL Design File from Current File.
- Choose either Verilog or VHDL as the output format.
- After the conversion, please use the generated HDL files in place of the original BDF modules.
I've attached the connection after replacing the .bdf file with the generated .v file for your reference. The attachment is named replacing_bdf_with_verilog_connection.png.
- Use Quartus Prime Standard Edition
You can also use for the Quartus Prime Standard Edition. I have tested the design with it and the SystemVerilog design able to instantiate BDF successfully. The Quartus Version that I am using was Quartus Prime Standard Edition 24.1. I have attached the connection diagram for your reference. The attachment is named quartus_standard_connection.png
We sincerely apologize for the inconvenience. Please feel free to let us know if you have any other questions.
Best regards,
ZiYingE_Altera
Occasional ContributorHi Zi Ying,
Thank you for detailed workaround methods.
You discovered that Quartus Standard version doesn't have this issue.
I didn't know that.
For "Create HDL Design File from Current File" workaround, it works for two-dimensional signals.
It is good for me.
For "Use Quartus Prime Standard Edition" workaround, my target device of actual project is Cyclone 10 GX, so this workaround is not available.
Please see my another post for my real project:
https://community.altera.com/discussions/quartus-prime/error13135-addresscommand-pin-is-constrained-to-an-illegal-location/353620/
This strange error in the post has the same root as our discussion.
Masaru
- ZiYingE_Altera
Hi Masaru,
Thank you for the additional details.
After discussing with the Altera design team again, there is currently no better workaround than using ".Out({<<{Out}})" for two dimensional signals, as BDF is no longer supported starting from Quartus Prime Pro Edition 23.3.
Based on your previous post, may I check a few additional details?
1. Does the original design that reports the following error contain a BDF module in its hierarchy?Error(13135): Address/command pin (ddr3_a[0]) is constrained to an illegal location (PIN_AG19). The legal location for this pin is PIN_Y17
2. When testing the DDR3 example design targeting the Cyclone 10 GX Development Kit that fails without error, was the same BDF module or hierarchy used?
Thank you!
Best regards,
ZiYingE_Altera- MamaSaru
1. Does the original design that reports the following error contain a BDF module in its hierarchy?
Yes, please see my experiment #8. and #10. for detail.
2. When testing the DDR3 example design targeting the Cyclone 10 GX Development Kit that fails without error, was the same BDF module or hierarchy used?
No, the example design from altera is not .sv to .bdf hierarchy structure.
