Connecting nodes without wires

My Dell Latitude only has 1.5GB free, less than 6GB total.

Is the schematic entry that much better in the new version? I'm an old tech and no savy HDL lingo.

My design is fairly simple:

An octal two to one mux, sixteen JK's, sixteen D's, an octal transparent latch, an eight input OR, eight two input NAND's. This is my first attempt, so I have no idea what device it will fit.

The existing discrete (asnchronous logic) design is a four channel ignition timing controller. I'm trying to update it to an eight channel system.

Pic of existing system:

http://www.jandssafeguard.com/images/4chproto.jpg

The digital part of the four channel design uses 12 dips. Eight channel discrete surface mount would be a chore, so here I are.

Is it stated that double-clicking on a wire is supposed to highlight the other wires with the same name? I don't think this was ever supposed to happen(it does highlight the entire net it is physically connected to, but not the ones connected by name alone). In the lock_detect design, if you type Ctrl-F and search on pll_clk, it highlights both nets.

Note that double-clicking on a net is probably not the best way to find non-connected signals. The user would have to click on every net. Probably the best way for a generic search is to look at messages to see what logic gets removed(because of unconnected nets). The RTL viewer should work if you're looking for a specific net, but it sounds like you already know they're not connected since Ctrl-F can find one and not the other, i.e. they have different names. If you're certain they are the same, something strange is going on that needs to be debugged, rather than more tests on whether they're connected. (The schematic entry tool is probably not astoundingly better in the latest version of Quartus, but it's always a good idea to upgrade when you can.) Good luck.

I must add in on this discussion as this is one of the topics that I am very strongly positioned on.

There are basically two camps of thought here.

1. The purpose of the drawing (schematic) is simply to obtain the interconnectivety of the signals by someone who knows what they are intending to connect and provide an efficeient way to pass that connectivity to a place and route tool.

2. The purpose of a drawing (schematic) is to provide a clear understanding of the interconnection of the varous sub elements within the design so that future people who refer to the drwawing can easily tell what is going on.

As I believe that all engineers really create is paperwork (electronic or otherwise) to document (capture) their design thoughts (so that others can actually execute upon it, be it another person or a computer), then I fall into# 2 above.

If you have ever had to dig in and figure out what is going on in one of those 'schematics' where all you have is big squares and stubby lines with signal names on them, you know what I am talking about.

Proper planning and thought (engineering) before you start 'dropping squares drawing lines' will provide half a chance that the structure and flow will be clarfiied by the drawing you are creating (and the lab technician will thank you 100 times over).

I say you draw the lines between the elements in you design with left to right signal flow (and place <-- reverse arrows to indicate any place where reverse signal flow occurs on the page).

In the end, you will have a well documented, easy to follow representation of your intended design (oh, and something that the P&R tool will turn into a working design).

Just my thoughts.

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When in doubt, do both. I'm the designer and the tech. Schematic entry to get the design into CPLD, then print it out and use it to fix bad boards. Oh, forgot. All the chips are inside.

So, you are saying to draw all the wires, not to rely on naming nodes for those on the other side of the page?

This goes for the common clock and presets and clears. too? Drawing area is big enough, so I'll just make room for the wires and call it good for now.