Confused over division by shifting

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Hi,

Suppose I have an array x whose 1st element x1 is a logic vector of length 8 and the second element x2 is also a logic vector of length 8 making the array x a logic vector of total length equals to 16. I have another array y whose 1st element y1 is a logic vector of length 16 and the second element y2 is also a logic vector of length 16 making the array y a logic vector of total length equals to 32. I want to perform a division of 2 by shifting the bits (15 downto 8) from y2 and storing it into x2. Will this give a division of 2 as I expected ? Can anyone help me clear this confusion of mine ? Please note that I'm not willing to use the normal division as I need to do more processing after this step.

Thanks,

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Your issue is not clear. If you want divide any vector by 2 you discard one lsb (i.e. bit(0)), or by 4 you discard 2 LSBs and so on (n of 2^n).

Hi Kaz,

Thanks for your reply. But what if I want to take a 16 bit logic vector want to store it in a 8 bit logic vector so that the result is division by 2 ?

Thanks,

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Hi Kaz,

Thanks for your reply. But what if I want to take a 16 bit logic vector want to store it in a 8 bit logic vector so that the result is division by 2 ?

Thanks,

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You need to determine the problem scope.

1) Does the maximum value you want to see fit within 8 bits? If it doesn't, what information are you willing to lose?

2) Do you need accuracy? If you drop multiple bits, are you rounding?

3) Are you actually looking for division by 2? Are you doing math on a signal or logic manipulation?

Hi Kaz and derim,

Thanks for your response. I'm willing to loose the 8 LSB as I'm only concerned about the 8 MSB ( 15 down to 8 ). I found one code in a book which is as follows :

Architecture abc of filter is

Type A0 is ARRAY (0 to 1) of SLV1; ---- SLV1 - logic vector of (7 downto 0 )

Type A1 is ARRAY (0 to 1) of SLV2; ---- SLV2 - logic vector of (15 downto 0 )

Signal f : A0;

Signal xemu : A1;

Begin

process1 : process (clk)

begin

f(1) <= xemu(1)(15 downto 8 ) ---- divide by 2 ( Here it says that it's getting divided by 2 )

end process;

end abc;

That was really confusing for me . Could you please kindly clear my confusing over this ?

Thanks,

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process1 : process (clk)

begin

f(1) <= xemu(1)(15 downto 8 ) ---- divide by 2 ( Here it says that it's getting divided by 2 )

end process;

end abc;

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This doesn't make much sense, as it isn't really a divide by 2 operation unless the bits don't represent a complete number-- for example the lower 8 bits represent a fractional portion (fixed-point). If you drop 8 bits, this would be dividing by 256. I wonder if they are thinking "divide by 2" as in the bit-width alone.

This code won't work well either way as the sensitivity list is "clk", not xemu, so this won't be able to function correctly in most simulators. if the process was "if(rising_edge(clk)) then", it would make sense, or instead having "process(xemu)" to instantiate pure combinatorics.

Hi derim,

That's what I was thinking too. Another question, what do you mean when you say "I wonder if they are thinking "divide by 2" as in the bit-width alone.", Could you please kindly explain this to me ?

Thanks,

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Hi derim,

That's what I was thinking too. Another question, what do you mean when you say "I wonder if they are thinking "divide by 2" as in the bit-width alone.", Could you please kindly explain this to me ?

Thanks,

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Oh, just that it went from 16 bits down to 8. hence "divide-by-2". I don't know anyone who would say this though!

Hi derim,

Now I get it , but it's kind of weird that going from 16 to 8 bit and saying it's divide by 2. My initial thought was dividing the value by 2 but not dividing the number of bits by 2 and saying it "divide by 2". Thanks for the clarification.

Thanks,