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Altera_Forum
Honored Contributor
10 years agoConfused over division by shifting
Hi, Suppose I have an array x whose 1st element x1 is a logic vector of length 8 and the second element x2 is also a logic vector of length 8 making the array x a logic vector of total length e...
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- process1 : process (clk) begin f(1) <= xemu(1)(15 downto 8 ) ---- divide by 2 ( Here it says that it's getting divided by 2 ) end process; end abc; --- Quote End --- This doesn't make much sense, as it isn't really a divide by 2 operation unless the bits don't represent a complete number-- for example the lower 8 bits represent a fractional portion (fixed-point). If you drop 8 bits, this would be dividing by 256. I wonder if they are thinking "divide by 2" as in the bit-width alone. This code won't work well either way as the sensitivity list is "clk", not xemu, so this won't be able to function correctly in most simulators. if the process was "if(rising_edge(clk)) then", it would make sense, or instead having "process(xemu)" to instantiate pure combinatorics.