Confused by timequest timing analyser

I am confused by timequest timing analyser too

1. ------------------------------------------

QII gives the following critical warning:

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From CLK24 (Rise) to CLK24 (Rise) (hold)

However, the SDC file definitely has the derive_clock_uncertainty command. What should I do? Should I add this command second time?

2. ------------------------------------------

sdc and timequest api reference manual (http://www.altera.com/literature/manual/mnl_sdctmq.pdf) does not describe virtual clocks. The create_clock command description states that <target> must be specified:

create_clock [-add] [-name <clock_name>] -period <value> [-waveform <edge_list>]

<targets>

I am confused with virtual clocks. Somewhere I've red that I should use virtual clocks in the set_input_delay and set_output_delay commands. But I am not sure that I've created virtual clocks correctly. Should virtual clocks somehow relate to real clocks?

3. ------------------------------------------

Some SDC commands can use -add or -add_delay options. I am not sure when should I use this option. For instance, set_input_delay description in the API RefMan reads

-add_delay: Add to existing delays instead of overriding them

Does it mean that I can use only the very first set_input_delay command without -add_delay option?