components connection

Hello there ,

In the top module (progetto.vhd), you can use the signal to connect the ports in the component instantiation. Also if you want the port out in the top module ,you can connect the top port to same signal. Then synthesis tool infer the signal using buffer.

I attached modified top module ( progetto.vhd) and synthesized schematic block diagram for your reference.

In case if you dont want to instantiate both the slowdown/updown port , you can comment below two lines in top module.

slowClock <= updown_slowclk_sig;

updown <= updown_slowclk_sig;

Thank you ,

Regards,

Sree