Forum Discussion

anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

Compile a design from a copy of its qsys

Hi all, I want to use a qsys file that is mostly a copy of a previous version of the same project. I have a design that I can synthesize and implement on an Arria10 FPGA but due to obsolescence of a...
Hdl
Platform
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Is the .qsys your top-level design or are you instantiating the system in a higher-level design?

What files are listed under Add/Remove files and in the Timing Analyzer settings (.sdc files)?

anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

The qsys belongs to the top-level.

I have no files listed in the sdc file, just setting constraints and setting clock groups for the IPs used within the project. Under Add/remove Files, the following are listed: some qsys files for the IPs used in the project, 2 qip files for the IP's that are bought from other companies, top-level VHDL file, the sdc file.