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dsun01's avatar
dsun01
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3 years ago
Solved

compilation warning message

Dear Support/Expert

I have a lot of warning message while I am compiling a JESD204B project.

It may related to CDF constrain. I am learning the timing analyzer now.

if as descripted in the warning, a rx_pma_clk was not created. the function of related logic will not work, am I right? in this case, any suggestion how to fix this problem

thank you,

David

Warning(332087): The master clock for this clock assignment could not be derived. Clock: jesd204b_inst|jesd_top_qsys_0|jesd_top_qsys_0|u_jesd_top_inst|JESD_RX.u_jesd_top_rx|jesd_dec_xcvr_0|RX_XCV.i1_xcvr_jesd_rx|jesd204_0|jesd204_0|inst_phy|inst_xcvr|g_xcvr_native_insts[1]|rx_pma_clk was not created.

  • skbeh's avatar
    skbeh
    3 years ago

    Hi David

    Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.

    https://www.intel.com/content/www/us/en/docs/programmable/683113/

    Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.

    See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'


    Regards

    Soon


6 Replies

  • skbeh's avatar
    skbeh
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    3 years ago

    Hi David


    1) You are using which Quartus version? Have you regenerated the JESD204B IP core prior to design compilation?


    2) Are you just using the JESD204B generated core in your design, or are you using the full JESD Example Design that is generated (including the transport layer from the example design)?


    3) As an experiment, please use the .sdc file generated with the IP. In this way, we can ensure that we are not missing a constraint, the concern is that all the needed .sdc constraints might not being used.


    4) Have you modified the clock names in the JESD SDC to match those in your actual design?

    Please refer to the steps described in the section '3.8.4. Timing Constraints For Input Clocks' of the JESD User Guide.

    https://www.intel.com/content/www/us/en/docs/programmable/683442/


    5. If your particular JESD variants will generate an Example Design from the IP GUI, can you ensure that you are not seeing timing violations in that as well? The Example Designs should be timing-clean.


    Regards

    Soon


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Soon,

      Thank you very much for the detailed suggestion. I will check all the items you mentioned above. It will take some time. I will get back to you after I get some result.

      Appreciate your help.

      David

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Soon,

      I am using 21.3 Quartus Prime version 21.3.0 build 170. if the JESD204B core is instantiated in a higher level .qsys and when I generate this high level module. will the Design Platform automatic regenerate all the sub modules/cores? if not, then I should regenerate all the cores that inside me top .qsys.

      thank you,

      David

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    3 years ago

    Hi David

    Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.

    https://www.intel.com/content/www/us/en/docs/programmable/683113/

    Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.

    See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'


    Regards

    Soon


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Skbeh,

      Here are some tests I did to understand how the time analysis works.

      1. I use Design Platform generate a example in the Presets( JESD204B example Design ( LMF= 888, 6.144Gbps). everything ran perfect.

      2. I changed the parameter to L = 4, M = 16, F = 8, N = 16, N' = 16, S = 1, K = 20. after this update the Generate Example Design button is not supported anymore, because the Available Example Designs Select Design is not changeable anymore( greyed out NONE).

      3. so I ran Generate HDL directly.

      4. after fixed minor pin assignment issue, the synthesis and fitter pass, but timing analysis will generate

      " The master clock for this clock assignment could not be derived. Clock: u_altjesd_ed_qsys_RX_TX|altjesd_ss_rx-tx|altjesd_rx_tx|g_xcvr_native_insts[0]|rx_pma_clk was not created. "

      I don't know how to reuse the .sdc file from the default example to my own Jesd setup. I am learning how to understand .sdc file. if you are familiar with time constrains, please give me some suggestions.

      Thank you very much,

      David

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Soon,

      I think I kind of understand the problem. I got the project from Texas Instrument; it was Arria V and Quartus 18. I made a lot of updates and modifications, so some signals or pins are different to the signal name in the .sdc file.

      I need to match the true signal name and the constrains of the .sdc file.

      while I am read the Quartus user manual. could you please recommend good tutorial/material for me to learn how the .sdc file works faster?

      thank you very much.

      David