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Contributorcompilation warning message
Hi David
Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.
https://www.intel.com/content/www/us/en/docs/programmable/683113/
Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.
See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'
Regards
Soon
ContributorHi David
1) You are using which Quartus version? Have you regenerated the JESD204B IP core prior to design compilation?
2) Are you just using the JESD204B generated core in your design, or are you using the full JESD Example Design that is generated (including the transport layer from the example design)?
3) As an experiment, please use the .sdc file generated with the IP. In this way, we can ensure that we are not missing a constraint, the concern is that all the needed .sdc constraints might not being used.
4) Have you modified the clock names in the JESD SDC to match those in your actual design?
Please refer to the steps described in the section '3.8.4. Timing Constraints For Input Clocks' of the JESD User Guide.
https://www.intel.com/content/www/us/en/docs/programmable/683442/
5. If your particular JESD variants will generate an Example Design from the IP GUI, can you ensure that you are not seeing timing violations in that as well? The Example Designs should be timing-clean.
Regards
Soon
ContributorHi Soon,
I am using 21.3 Quartus Prime version 21.3.0 build 170. if the JESD204B core is instantiated in a higher level .qsys and when I generate this high level module. will the Design Platform automatic regenerate all the sub modules/cores? if not, then I should regenerate all the cores that inside me top .qsys.
thank you,
David
