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dsun01's avatar
dsun01
Icon for Contributor rankContributor
3 years ago
Solved

compilation warning message

Dear Support/Expert I have a lot of warning message while I am compiling a JESD204B project. It may related to CDF constrain. I am learning the timing analyzer now. if as descripted in the ...
  • skbeh's avatar
    skbeh
    3 years ago

    Hi David

    Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.

    https://www.intel.com/content/www/us/en/docs/programmable/683113/

    Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.

    See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'


    Regards

    Soon


skbeh's avatar
skbeh
Icon for Contributor rankContributor
3 years ago

Hi David

Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.

https://www.intel.com/content/www/us/en/docs/programmable/683113/

Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.

See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'


Regards

Soon