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Contributorcompilation warning message
Hi David
Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.
https://www.intel.com/content/www/us/en/docs/programmable/683113/
Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.
See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'
Regards
Soon
ContributorHi David
Based on the design example generated from JESD204B Intel Arria 10 FPGA IP Design Example User Guide below. The design example will include top level design constraints file.
https://www.intel.com/content/www/us/en/docs/programmable/683113/
Users can modify the clock constraints in the SDC constraints file (altera_jesd204_ed_<data path>.sdc) to reflect their new clock frequency values.
See section '1.2.11.2. Changing the Data Rate or Reference Clock Frequency'
Regards
Soon
dsun01Hi Skbeh,
Here are some tests I did to understand how the time analysis works.
1. I use Design Platform generate a example in the Presets( JESD204B example Design ( LMF= 888, 6.144Gbps). everything ran perfect.
2. I changed the parameter to L = 4, M = 16, F = 8, N = 16, N' = 16, S = 1, K = 20. after this update the Generate Example Design button is not supported anymore, because the Available Example Designs Select Design is not changeable anymore( greyed out NONE).
3. so I ran Generate HDL directly.
4. after fixed minor pin assignment issue, the synthesis and fitter pass, but timing analysis will generate
" The master clock for this clock assignment could not be derived. Clock: u_altjesd_ed_qsys_RX_TX|altjesd_ss_rx-tx|altjesd_rx_tx|g_xcvr_native_insts[0]|rx_pma_clk was not created. "
I don't know how to reuse the .sdc file from the default example to my own Jesd setup. I am learning how to understand .sdc file. if you are familiar with time constrains, please give me some suggestions.
Thank you very much,
David
- dsun01
Hi Soon,
I think I kind of understand the problem. I got the project from Texas Instrument; it was Arria V and Quartus 18. I made a lot of updates and modifications, so some signals or pins are different to the signal name in the .sdc file.
I need to match the true signal name and the constrains of the .sdc file.
while I am read the Quartus user manual. could you please recommend good tutorial/material for me to learn how the .sdc file works faster?
thank you very much.
David
