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ABoel
New Contributor
New ContributorCompilation freezes at 2% when compiling verilog code
Intel Quartus 18.1 Build 625 compilation freezes at 2% when code snippet below is present in the Verilog code. bgr_data[23:16]<=data_ROM[count]; I have modified the code VGA_Pattern project provi...
ABoelNew Contributor
New ContributorKhaiY,
I think the size of the memory may not be appropriate for the MAX 10 FPGA. I will change the project to use the SDRAM then I can initialize it with the RGB. That should hopefully work.
