ABoel
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5 years agoCompilation freezes at 2% when compiling verilog code
Intel Quartus 18.1 Build 625 compilation freezes at 2% when code snippet below is present in the Verilog code.
bgr_data[23:16]<=data_ROM[count];I have modified the code VGA_Pattern project provided with DE10-Lite to load hex RGB data from a file and during the display interval it shall access the data_ROM at a dynamic index that incrments on every horizontal synch interval.
The Array has been defined as per below.
reg [7:0] data_ROM [0:(3*640*480)-1];
initial begin
$readmemh("vgah.mem", data_ROM);
endI tried several variants to access to access the data form the data_ROM but the compiler keeps looping at 2%.