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Shriraksha's avatar
Shriraksha
Icon for New Contributor rankNew Contributor
1 year ago

Compilation Error in Quartus Prime Pro 24.1

Error: Unable to create log file questasim_verilog_no_rtl

Error: couldn't open "questasim_verilog_no_rtl": permission denied

Error: Compilation was NOT successful. 2 errors, 0 warnings

These are the errors obtained while compiling the verilog HDL code in Quartus Prime Pro 24.1 using questasim tool. Please provide the solution.

Thank You

Simulation

3 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    May I know if the issue has been resolved and if you still need help with this case?


    Regards,

    Richard Tan


    • Shriraksha's avatar
      Shriraksha
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      The issue has been resolved.

      Thank you

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    I'm pleased to know that your question has been addressed.

    Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you and have a great day!

    Best Regards,

    Richard Tan