there are some warnings in my design during compilation and simulation.
1. Compilation Warning (10230): Verilog HDL assignment warning at clk_generator.v(16): truncated value with size 32 to match size of target (13).
question: I already declare the signal as 13 bits. Why do I still receive this kind of warnings? How to solve it?
- Timing Simulation Warning: Can't display state machine states -- register holding state machine bit "|UART|C_receive:U_C_receive|ps.s1" was synthesized away
question: May I know what is the reason to cause this kind of warning? How to solve it? The code is shown below
module C_receive (clk_1Mhz, reset, get_data, rdrf, r_x_ready_in, ready_in);
input clk_1Mhz, reset;
input get_data;
input rdrf;
output reg r_x_ready_in;
output reg ready_in;
reg [1:0] ps, ns;
parameter [1:0] s0 = 0, s1 = 1, s2 = 2, s3 = 3;
always @ (ps or get_data or rdrf)
begin
case (ps)
s0: begin r_x_ready_in = 1; ready_in = 0;
if (rdrf)
ns = s0;
else if (get_data)
ns = s1;
else
ns = s0;
end
//--------------------------------------------------------
s1: begin r_x_ready_in = 0; ready_in=0;
if (rdrf)
ns = s2;
else
ns = s1;
end
//----------------------------------------------------------
.
.
- timing simulation: clock receiver waveform have lots of glitches in UART_comm which is intermediate module. However, there is no glitch in clock_generator module (lowest module)and UART(top module) when timing simulation were done. Can anyone explain on it?
Warning: Ignored node in vector source file. Can't find corresponding node name "UART_transmitter:U_UART_Transmitter|Transmitter_CU:U_Transmitter_CU|byte_ready" in design.
background: There is something wrong in my simulation. So, in order to find it out , I try to check and insert the intermediate signal through node finder (subentities).
question: Can somebody let me know the reason that can’t find the node.? it suppose should have. * Some of the intermediate signal can be shown in waveform.
Thanks a lot.
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