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1. Compilation Warning (10230): Verilog HDL assignment warning at clk_generator.v(16): truncated value with size 32 to match size of target (13).
question: I already declare the signal as 13 bits. Why do I still receive this kind of warnings? How to solve it?
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You need to show the code for this
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- Timing Simulation Warning: Can't display state machine states -- register holding state machine bit "|UART|C_receive:U_C_receive|ps.s1" was synthesized away
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Your code fragment doesn't show where ps is being set. I'd expect to see something like:
always @(clock or resetn) begin
if ( ~resetn )
ps <= 2'b00;
else
ps <= ns;
end
If this code isn't there, then ps will be assumed as constant zero and then it's likely to be optimized away.
Honored Contributor
