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Altera_Forum's avatar
Altera_Forum
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11 years ago

compairing signals inside a clock sensitive process

Hi!

This code is a simplification of the actual code. clk is a 50Mhz clock signal, busy is an of chip signal coming from one of the pins. (GPIO on the DE2-115 developing board)

busy_i is an internal signal and n is just a signal used to count clock periodes.

process(clk)

begin

busy_i <= busy;

n <= n + 1;

if((busy_i = '1') and (busy = '0')) then

state <= s_RD;

elsif(n = 1500) then

state <= s_RD;

end if;

end process;

This code wil not always detect the falling edge on busy(the difference in busy_i and busy).

That is also why i included the elsif statment, so that after a given count of clock periodes the state signal vil be forced the value of s_RD.

So my question is: Is this some bad coding from me, or could it be somthing with the fact that busy is an of chip signal - maybe a combination of the two?

Realy appreciate some thoughts! Maybe someone have hade a similar issue?

Thanks!

-electrosmith

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You forget the rising_edge(clk) !! 

    
process(clk)
begin
if rising_edge(clk) then
   busy_i <= busy;
   n <= n + 1;
   if((busy_i = '1') and (busy = '0')) then
      state <= s_RD;
   elsif(n = 1500) then
      state <= s_RD;
   end if;
end if;
end process;

    Moreover, insert at least 2 D flip fop on your "busy" signal to prevent metastability
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    heh:P yes the missing rising_edge() is just a typo, its not missing in the actual code:) But thanks for the heads-up about metastability, wil add a couble of DFF's to my signal and see if it helps;)