Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

compairing signals inside a clock sensitive process

Hi! This code is a simplification of the actual code. clk is a 50Mhz clock signal, busy is an of chip signal coming from one of the pins. (GPIO on the DE2-115 developing board) busy_i is an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

heh:P yes the missing rising_edge() is just a typo, its not missing in the actual code:) But thanks for the heads-up about metastability, wil add a couble of DFF's to my signal and see if it helps;)