compairing signals inside a clock sensitive process

You forget the rising_edge(clk) !!

process(clk)
begin
if rising_edge(clk) then
   busy_i <= busy;
   n <= n + 1;
   if((busy_i = '1') and (busy = '0')) then
      state <= s_RD;
   elsif(n = 1500) then
      state <= s_RD;
   end if;
end if;
end process;