combinational delayline

Hi,

hope someone knows the answer to this one.

The basis of my design is a compinational delayline made from buffers from an input pin to an output pin with each buffer tapped into the D of a Dtype reg.

I have 4 delaylines and they must be of the same timing. I have an empty stratix III to perform this starting point where I will then lock the cells and routing for the rest of the design.

Try as I may I cannot get these 4 circuits to be the same as the router seems to arbitarly place the design. How can I tell the router that these are critcal paths. There are no clocks or set and hold timing as this delay is purely combinational.

Thanks

Robert