Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

combinational delayline

Hi, hope someone knows the answer to this one. The basis of my design is a compinational delayline made from buffers from an input pin to an output pin with each buffer tapped into the D of a Dt...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You could try by specifying an 'impossible' Tpd from input to output. The router will try its best.