Altera_Forum
Honored Contributor
8 years agoCode conversion
Currently working in Verilog, and it was requested my program be converted to SystemVerilog. Can anyone help me translate:confused: the two languages?
I'm no expert, but there is a deeper answer if you really want , but why risk it if it already works and the benefits feels minuscule, especially with altera and if the point being to be able to compile the design for a newer ic or something..