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Altera_Forum's avatar
Altera_Forum
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8 years ago

Code conversion

Currently working in Verilog, and it was requested my program be converted to SystemVerilog. Can anyone help me translate:confused: the two languages?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Congratulations you are already done. Easiest project you will ever have. Verilog is a proper subset of SystemVerilog, by design, so your verilog code should work as is.