Clocking is too complex - error

Please advise me how to get rid of error from the title. It appears when I try to compile following code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ff IS
PORT(
t : IN std_logic;
s : IN std_logic;
r : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic);
END ff;
ARCHITECTURE behavior OF ff IS
SIGNAL qs : std_logic;
BEGIN
PROCESS(r,s,t)
BEGIN
IF (r='0') THEN
    qs<='0';
ELSE
    IF (s='0') THEN
        qs<='1';
    ELSE
        IF (rising_edge(t)) THEN
            qs<=not(qs);
        END IF;
    END IF;
END IF;
END PROCESS;
q <= qs;
qi <= not(qs);
END behavior;