Clock pessimism removal

SyafieqS,

I prepared a minimal design showing the phenomenon. The topology is still as mentioned in my first post, however, I reduced the number of data lanes to 2 and removed all signal treatment and control.

You should especially look at the setup and hold timing of the "from: i_slv2_ser4*" data lane inputs. Without removing the common clock path pessimism introduced by the common Main pll, the timing analyzer will always show failed timing...

Also on other paths the design fails due to the not removed clock pessimism....

I hope you can help me!

Thank you

Christoph Dietz