Forum Discussion

ChristophD's avatar
ChristophD
Icon for New Contributor rankNew Contributor
5 years ago

Clock pessimism removal

I need to time constrain a source-synchronous interface between a Cyclone10GX and a LVDS camera interface running at ~596MBPS. (I'm using Quartus prime pro 19.3) The FPGA drives out a 124MHz clk ...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Chris,


Can you share the design file that suppose to show the removed timing pessimism?

Attached the qar here.


  • ChristophD's avatar
    ChristophD
    Icon for New Contributor rankNew Contributor
    5 years ago

    SyafieqS,

    I prepared a minimal design showing the phenomenon. The topology is still as mentioned in my first post, however, I reduced the number of data lanes to 2 and removed all signal treatment and control.

    You should especially look at the setup and hold timing of the "from: i_slv2_ser4*" data lane inputs. Without removing the common clock path pessimism introduced by the common Main pll, the timing analyzer will always show failed timing...

    Also on other paths the design fails due to the not removed clock pessimism....

    I hope you can help me!

    Thank you

    Christoph Dietz