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Altera_Forum's avatar
Altera_Forum
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18 years ago

clock enable multicycle

Hi,

I assign a "clock enable source multicycle" requirement to a path from FSM1:FSM_level1|clken to add_sub_level1|clken.

I added also the attribute :

<attribute direct_enable : boolean;

<attribute direct_enable of clken :signal is true;

in the add_sub_level1| VHDL code

Synthesis is OK, but the assignment is removed.

I get this message in the compilation report :

Node named add_sub:add_sub_level1|clken removed during synthesis.

How can I do to avoid the synthesizer to remove this node ?

roberts

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Why is it getting removed? It's usually:

    - The source driving it gets removed

    - What it drives gets removed

    - It gets merged with an identical register

    And my guess is it's the third case. Search the .map.rpt messages for this register and see if it gives more information. Also look in the GUI report(same thing but easier to look through) for the optimization tabs.

    If it's removed because it's a duplicate, I usually add it to the Assignment Editor and the assignment Remove Duplicate Registers = Off.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Thanks for your answer.

    In fact I find nothings about this node in the optimization tabs.

    And when I do "Locate in RTL wiever", after synthesis, this node is found !

    roberts
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    RTL view is not post synthesis. It is an RTL view of the code you've written(i.e. before logic is pruned, merged, etc.). The technology view is after the synthesis, but now it is much harder to understand since it is just LUTs and Flip-Flops, which can be very hard to follow if you're trying to understand the RTL. That being said, go to the technology viewer, find one of the registers that this signal originally fanned out to, and trace back to what drives it now. This could be a good clue.

    Also, go to Assignments -> Settings -> Analysis & Synthesis -> More settings and increase the Number of Removed Registers Reported and redo synthesis. (This was recently added. Technically I'm not a big fan of it, but too many designs received 10,000+ messages like this that just cluttered everything too much)