clock enable multicycle

RTL view is not post synthesis. It is an RTL view of the code you've written(i.e. before logic is pruned, merged, etc.). The technology view is after the synthesis, but now it is much harder to understand since it is just LUTs and Flip-Flops, which can be very hard to follow if you're trying to understand the RTL. That being said, go to the technology viewer, find one of the registers that this signal originally fanned out to, and trace back to what drives it now. This could be a good clue.

Also, go to Assignments -> Settings -> Analysis & Synthesis -> More settings and increase the Number of Removed Registers Reported and redo synthesis. (This was recently added. Technically I'm not a big fan of it, but too many designs received 10,000+ messages like this that just cluttered everything too much)