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Altera_Forum's avatar
Altera_Forum
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18 years ago

clock enable multicycle

Hi, I assign a "clock enable source multicycle" requirement to a path from FSM1:FSM_level1|clken to add_sub_level1|clken. I added also the attribute : <attribute direct_enable : boolea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for your answer.

In fact I find nothings about this node in the optimization tabs.

And when I do "Locate in RTL wiever", after synthesis, this node is found !

roberts