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Altera_Forum's avatar
Altera_Forum
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15 years ago

Clock domain warning when using Signaltap with PCI Express example design

Hi, I'm working with the following configuration:

Quartus II 9.0 SP2 (64 bit) full version under Windows 7

PCI Express Development Kit Stratix II GX Edition

Chaining DMA Design Example generated by the PCI Express Compiler

The application layer uses the clk250_out clock signal generated by the PCI Express IP core. When I enable Signaltap with this clock, I get the following critical warning during compilation:

Critical Warning: Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB central clock divider.

From the submessages of this warning it appears that the problem is related to the altera_internal_jtag~TCKUTAP clock used by Signaltap. All the signals I'm trying to probe are synchronized to clk250_out.

I would appreciate any recommendations for getting Signaltap working with this design.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    I have the view that signaltap is based on dc dual port ram with one port for sampling data on its clock and the other port for signaltap clock (jtag clock) and hence the paths are cut for analysis possibly by default statements. Could it be your default statements are missing?

  • Altera_Forum's avatar
    Altera_Forum
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    Hi kaz, thank you for your response.

    Sorry, I'm not sure what you mean by "default statements" in this context, could you please clarify?
  • Altera_Forum's avatar
    Altera_Forum
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    I expect the Quartus to automate the timing constraints for signaltap (e.g. in sdc file). But apparently it is not doing that.

    Try this:

    write an initial sdc then compile your project then run TimeQuest and update netlist there. Then click on write sdc file.

    You should get sdc file for your project which will contain statements regarding false paths between clock domains. Then use that sdc file for your project.
  • Altera_Forum's avatar
    Altera_Forum
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    Switching to TimeQuest (I've been using Classic Timing Analyzer as it was the default setting) and applying your method solved my problem, thanks!