Altera_Forum
Honored Contributor
15 years agoClock domain warning when using Signaltap with PCI Express example design
Hi, I'm working with the following configuration:
Quartus II 9.0 SP2 (64 bit) full version under Windows 7 PCI Express Development Kit Stratix II GX Edition Chaining DMA Design Example generated by the PCI Express Compiler The application layer uses the clk250_out clock signal generated by the PCI Express IP core. When I enable Signaltap with this clock, I get the following critical warning during compilation: Critical Warning: Register-to-register paths between different clock domains is not recommended if one of the clocks is from GXB central clock divider. From the submessages of this warning it appears that the problem is related to the altera_internal_jtag~TCKUTAP clock used by Signaltap. All the signals I'm trying to probe are synchronized to clk250_out. I would appreciate any recommendations for getting Signaltap working with this design.