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Altera_Forum
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14 years ago

Clock domain warning when using Signaltap with PCI Express example design

Hi, I'm working with the following configuration: Quartus II 9.0 SP2 (64 bit) full version under Windows 7 PCI Express Development Kit Stratix II GX Edition Chaining DMA Design Example gene...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I have the view that signaltap is based on dc dual port ram with one port for sampling data on its clock and the other port for signaltap clock (jtag clock) and hence the paths are cut for analysis possibly by default statements. Could it be your default statements are missing?