Clock domain warning when using Signaltap with PCI Express example design

I expect the Quartus to automate the timing constraints for signaltap (e.g. in sdc file). But apparently it is not doing that.

Try this:

write an initial sdc then compile your project then run TimeQuest and update netlist there. Then click on write sdc file.

You should get sdc file for your project which will contain statements regarding false paths between clock domains. Then use that sdc file for your project.