Hey guys, I am trying to design a counter . First of all, i have a clock divider block which will take on-board clock of 50 Mhz and will change it into frequency of 1Hz. The output frequency of 1Hz goes into my counter block. I have separately checked my codes, they are simulating and are working fine, but when I am trying to combine my blocks, i see my output in seven segment display which shows a constant output. I don't know what to do. Need your help guys. Regards Muzz

how about posting some code. Btw, using logic clocks is not recommened. You should use clock enables isntead.

--- Quote Start --- how about posting some code. Btw, using logic clocks is not recommened. You should use clock enables isntead. --- Quote End --- Here goes the code : module clock_divide(clk_out,clk_50); input clk_50; output clk_out; reg[24:0] count; // to count 25 million you need 25 bit counter reg clk_out; parameter TC=25'd25000000-25'd1; initial begin count=0; clk_out=0; end always @(posedge clk_50) begin if (count==0)begin count <=TC; clk_out <=~clk_out; end else count<=count-1'b1; end endmodule module up_counter( out, enable , clk, reset ); output [7:0] out; input enable, reset, clk; reg [7:0] out; //-------------Code Starts Here------- always @(posedge clk) if (reset) begin out <= 8'h0 ; end else if (enable) begin out <= out + 1; end endmodule // hex to seven segment decoder module hexadecimalcounter(hex_1, hex_0, hex_num); input [3:0] hex_num; output[6:0] hex_1; output[6:0] hex_0; reg [6:0] hex_1; reg [6:0] hex_0; always @(hex_num) begin case (hex_num) 4'h0: {hex_1, hex_0} = {7'b1111111, 7'b1000000}; // 7-seg for 0 4'h1: {hex_1, hex_0} = {7'b1111111, 7'b1111001} ; // 7-seg for 1 4'h2: {hex_1, hex_0} = {7'b1111111, 7'b0100100} ; // 7-seg for 2 4'h3: {hex_1, hex_0} = {7'b1111111, 7'b0110000} ; // 7-seg for 3 4'h4: {hex_1, hex_0} = {7'b1111111, 7'b0011001} ; // 7-seg for 4 4'h5: {hex_1, hex_0} = {7'b1111111, 7'b0010010} ; // 7-seg for 5 4'h6: {hex_1, hex_0} = {7'b1111111, 7'b0000010} ; // 7-seg for 6 4'h7: {hex_1, hex_0} = {7'b1111111, 7'b1111000} ; // 7-seg for 7 4'h8: {hex_1, hex_0} = {7'b1111111, 7'b0000000} ; // 7-seg for 8 4'h9: {hex_1, hex_0} = {7'b1111111, 7'b0011000} ; // 7-seg for 9 4'ha: {hex_1, hex_0} = {7'b1111001, 7'b1000000} ; // 7-seg for A 4'hb: {hex_1, hex_0} = {7'b1111001, 7'b1111001} ; // 7-seg for B 4'hc: {hex_1, hex_0} = {7'b1111001, 7'b0100100} ; // 7-seg for C 4'hd: {hex_1, hex_0} = {7'b1111001, 7'b0110000} ; // 7-seg for D 4'he: {hex_1, hex_0} = {7'b1111001, 7'b0011001} ; // 7-seg for E 4'hf: {hex_1, hex_0} = {7'b1111001, 7'b0010010} ; // 7-seg for F default: {hex_1, hex_0} = {7'b1111001, 7'b1111111} ; // 7-segment code for blank endcase end endmodule // top level module counter_hexa module counter_hexa( enable, clk_50, reset, hex_1, hex_0, clk_out); input enable, clk_50, reset; output [7:0] hex_1, hex_0; output wire clk_out; wire [7:0] out; clock_divide ch_cd(clk_out,clk_50); up_counter ch_upc(clk_out, reset, enable, out); hexadecimalcounter ch_hxdc(out, hex_1, hex_0); endmodule Here is the code. Hope to hear from you soon.

how about using a PLL to divide the clock? but i am not sure whether this range of 1MHz is allowed or not. You may check with PLL

In your top level module, it looks to me like where you instantiate the module "up_counter", you have listed the ports in the wrong order. Same for the "hexadecimalcounter" instantiation. You are using the "ordered list" method of module instantiation. At the cost of some extra typing, you could instead use the "connect by name" method and be less likely to have problems of this sort. I think you may have some additional issues with your instantiation of "hexadecimalcounter". I am not clear on just what you are trying to achieve but the sizes of the signals you are connecting to the module are not the same as defined by the module. It also looks like your counter will count from 0 to 255 but the display will only go from 0 to 15.

--- Quote Start --- In your top level module, it looks to me like where you instantiate the module "up_counter", you have listed the ports in the wrong order. Same for the "hexadecimalcounter" instantiation. You are using the "ordered list" method of module instantiation. At the cost of some extra typing, you could instead use the "connect by name" method and be less likely to have problems of this sort. I think you may have some additional issues with your instantiation of "hexadecimalcounter". I am not clear on just what you are trying to achieve but the sizes of the signals you are connecting to the module are not the same as defined by the module. It also looks like your counter will count from 0 to 255 but the display will only go from 0 to 15. --- Quote End --- I am trying to achieve a hexadecimal counter which will count from 00 to FF. any additional comments or points to join in my code. What could be done to make it run ?

clock divider with counter | Altera Community

11 Replies

Altera_Forum

Honored Contributor

12 years ago

--- Quote Start ---

The port connections are still incorrect. You should follow mvanpelt's suggestion and use named ports during the instantiation. By being more explicit, it will show you some of your mistakes.

e.g.

This:


up_counter ch_upc
(
  .clk         ( clk_out ),
  .enable      ( enable  ),
  .reset       ( reset   ),
  .out         ( out     )
);

vs.


module up_counter(clk, enable, reset, out );
...
endmodule;
up_counter ch_upc(clk_out, reset, enable, out);

--- Quote End ---

my code is working now..but still some issue...i have two seven segments in my FPGA board..value at one's place is counting from 0 to F but value at ten's place is showing irregular values..i m posting the code which shows 0 to F in one's place but nothing much on ten's place...


case (out)
8'h0: {hex_0, hex_1} = {7'b1111111, 7'b1000000}; // 7-seg for 0
8'h1: {hex_0, hex_1} = {7'b1111111, 7'b1111001} ; // 7-seg for 1
8'h2: {hex_0, hex_1} = {7'b1111111, 7'b0100100} ; // 7-seg for 2
8'h3: {hex_0, hex_1} = {7'b1111111, 7'b0110000} ; // 7-seg for 3
8'h4: {hex_0, hex_1} = {7'b1111111, 7'b0011001} ; // 7-seg for 4
8'h5: {hex_0, hex_1} = {7'b1111111, 7'b0010010} ; // 7-seg for 5
8'h6: {hex_0, hex_1} = {7'b1111111, 7'b0000010} ; // 7-seg for 6
8'h7: {hex_0, hex_1} = {7'b1111111, 7'b1111000} ; // 7-seg for 7
8'h8: {hex_0, hex_1} = {7'b1111111, 7'b0000000} ; // 7-seg for 8
8'h9: {hex_0, hex_1} = {7'b1111111, 7'b0010000} ; // 7-seg for 9
8'ha: {hex_0, hex_1} = {7'b1111001, 7'b0001000} ; // 7-seg for A
8'hb: {hex_0, hex_1} = {7'b1111001, 7'b0000011} ; // 7-seg for B
8'hc: {hex_0, hex_1} = {7'b1111001, 7'b1000110} ; // 7-seg for C
8'hd: {hex_0, hex_1} = {7'b1111001, 7'b0100001} ; // 7-seg for D
8'he: {hex_0, hex_1} = {7'b1111001, 7'b0000110} ; // 7-seg for E
8'hf: {hex_0, hex_1} = {7'b1111001, 7'b0001110} ; // 7-seg for F
  endcase	
  end 
  endmodule

I am just posting the code in which I am facing problem. As i said value corresponding to hex_0 works fine, iterating from 0 to F but no change in hex_0. It either remains constant or not even changes.

Hope to hear from you soon.

Forum Discussion

clock divider with counter

11 Replies

Recent Discussions

How can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?

timing violation fix

Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10

Using Quartus with softHSM

The quartus license works with version 25.0 but not with version 17.0