--- Quote Start ---
The port connections are still incorrect. You should follow mvanpelt's suggestion and use named ports during the instantiation. By being more explicit, it will show you some of your mistakes.
e.g.
This:
up_counter ch_upc
(
.clk ( clk_out ),
.enable ( enable ),
.reset ( reset ),
.out ( out )
);
vs.
module up_counter(clk, enable, reset, out );
...
endmodule;
up_counter ch_upc(clk_out, reset, enable, out);
--- Quote End ---
my code is working now..but still some issue...i have two seven segments in my FPGA board..value at one's place is counting from 0 to F but value at ten's place is showing irregular values..i m posting the code which shows 0 to F in one's place but nothing much on ten's place...
case (out)
8'h0: {hex_0, hex_1} = {7'b1111111, 7'b1000000}; // 7-seg for 0
8'h1: {hex_0, hex_1} = {7'b1111111, 7'b1111001} ; // 7-seg for 1
8'h2: {hex_0, hex_1} = {7'b1111111, 7'b0100100} ; // 7-seg for 2
8'h3: {hex_0, hex_1} = {7'b1111111, 7'b0110000} ; // 7-seg for 3
8'h4: {hex_0, hex_1} = {7'b1111111, 7'b0011001} ; // 7-seg for 4
8'h5: {hex_0, hex_1} = {7'b1111111, 7'b0010010} ; // 7-seg for 5
8'h6: {hex_0, hex_1} = {7'b1111111, 7'b0000010} ; // 7-seg for 6
8'h7: {hex_0, hex_1} = {7'b1111111, 7'b1111000} ; // 7-seg for 7
8'h8: {hex_0, hex_1} = {7'b1111111, 7'b0000000} ; // 7-seg for 8
8'h9: {hex_0, hex_1} = {7'b1111111, 7'b0010000} ; // 7-seg for 9
8'ha: {hex_0, hex_1} = {7'b1111001, 7'b0001000} ; // 7-seg for A
8'hb: {hex_0, hex_1} = {7'b1111001, 7'b0000011} ; // 7-seg for B
8'hc: {hex_0, hex_1} = {7'b1111001, 7'b1000110} ; // 7-seg for C
8'hd: {hex_0, hex_1} = {7'b1111001, 7'b0100001} ; // 7-seg for D
8'he: {hex_0, hex_1} = {7'b1111001, 7'b0000110} ; // 7-seg for E
8'hf: {hex_0, hex_1} = {7'b1111001, 7'b0001110} ; // 7-seg for F
endcase
end
endmodule
I am just posting the code in which I am facing problem. As i said value corresponding to hex_0 works fine, iterating from 0 to F but no change in hex_0. It either remains constant or not even changes.
Hope to hear from you soon.
Honored Contributor
