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After you have addressed the comments raised by mvanpelt (primarily the port connections being incorrect), try posting your code again and a description of how it is broken / what you have fixed since the previous post.
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I am trying to make a counter which will count from 00 to FF and will display it in seven segment on my board.
I am re-posting code. I have done bit of re-ordering as mvanpelt said. Still i see the same output. I should see my seven segment counting but the output shown at my display is 80 and when I simulate the code, i just see 00 and 40. I am trying to this from past 2 weeks and I think I am stuck forever.
Here is the code:
module clock_divide(clk_out,clk_50);
input clk_50;
output clk_out;
reg[24:0] count; // to count 25 million you need 25 bit counter
reg clk_out;
parameter TC=25'd25000000-25'd1;
initial begin
count=0;
clk_out=0;
end
always @(posedge clk_50)
begin
if (count==0)begin
count <=TC;
clk_out <=~clk_out;
end
else
count<=count-1'b1;
end
endmodule
module up_counter(clk, enable, reset, out );
output [7:0] out;
input enable, reset, clk;
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
out <= 8'h0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule
// hex to seven segment decoder
module hexadecimalcounter(hex_1, hex_0, hex_num);
input [3:0] hex_num;
output[6:0] hex_1;
output[6:0] hex_0;
reg [6:0] hex_1;
reg [6:0] hex_0;
always @(hex_num)
begin
case (hex_num)
8'h0: {hex_1, hex_0} = {7'b1111111, 7'b1000000}; // 7-seg for 0
8'h1: {hex_1, hex_0} = {7'b1111111, 7'b1111001} ; // 7-seg for 1
8'h2: {hex_1, hex_0} = {7'b1111111, 7'b0100100} ; // 7-seg for 2
8'h3: {hex_1, hex_0} = {7'b1111111, 7'b0110000} ; // 7-seg for 3
8'h4: {hex_1, hex_0} = {7'b1111111, 7'b0011001} ; // 7-seg for 4
8'h5: {hex_1, hex_0} = {7'b1111111, 7'b0010010} ; // 7-seg for 5
8'h6: {hex_1, hex_0} = {7'b1111111, 7'b0000010} ; // 7-seg for 6
8'h7: {hex_1, hex_0} = {7'b1111111, 7'b1111000} ; // 7-seg for 7
8'h8: {hex_1, hex_0} = {7'b1111111, 7'b0000000} ; // 7-seg for 8
8'h9: {hex_1, hex_0} = {7'b1111111, 7'b0011000} ; // 7-seg for 9
8'ha: {hex_1, hex_0} = {7'b1111001, 7'b1000000} ; // 7-seg for A
8'hb: {hex_1, hex_0} = {7'b1111001, 7'b1111001} ; // 7-seg for B
8'hc: {hex_1, hex_0} = {7'b1111001, 7'b0100100} ; // 7-seg for C
8'hd: {hex_1, hex_0} = {7'b1111001, 7'b0110000} ; // 7-seg for D
8'he: {hex_1, hex_0} = {7'b1111001, 7'b0011001} ; // 7-seg for E
8'hf: {hex_1, hex_0} = {7'b1111001, 7'b0010010} ; // 7-seg for F
endcase
end
endmodule
// top level module counter_hexa
module counter_hexa( clk_50, enable, reset, hex_1, hex_0);
input enable, clk_50, reset;
output [7:0] hex_1, hex_0;
wire clk_out;
wire [7:0] out;
clock_divide cd(clk_50, clk_out);
up_counter upc(clk_out, reset, enable, out);
hexadecimalcounter hxdc(out, hex_0, hex_1);
endmodule
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