Honored Contributorhi, everyone! I have an project with major clock freq of 125Mhz, generated by register from 250Mhz clock source. Data is tranfered from 125Mhz clock domain to 250Mhz clock domain, and setup slack is about -1.2ns. I have checked that the average clock delay of 125Mhz clock is 7.x ns. Meanwhile, clock delay in 250Mhz clock demain is 3.8 ns. How can I reduce the clock delay of 125Mhz clk? Thx! :)
Honored ContributorAre you generating a clock or a clock enable from the register? If you need to generate a clock, use a PLL.
Honored ContributorHonored ContributorFPGA's have relatively long, pre-built, clock distribution trees.
Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice. If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock. By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem.Honored ContributorHonored ContributorHonored ContributorIn normal mode, the PLL will compensate the clocks for the delay of the clock tree.
In other words, the PLL's output clock will be "ahead" of the input clock in such a way that, at the end of the clock tree, the PLL clock will be in phase with the input clock. derive_pll_clocks ^^ Add this, and TimeQuest will automatically create and constrain all the PLL output clocksHonored Contributor
