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FPGA's have relatively long, pre-built, clock distribution trees.
Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice.
If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock.
By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem.
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Q1:Why the delay between output and input of the pll is an negetive value?
https://www.alteraforum.com/forum/attachment.php?attachmentid=8036 Q2:I want to set the constraint of two outputs of the pll, but I can only find one clock ouput...
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