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Altera_Forum
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12 years ago

Clock delay is too long...

hi, everyone! I have an project with major clock freq of 125Mhz, generated by register from 250Mhz clock source. Data is tranfered from 125Mhz clock domain to 250Mhz clock domain, and setup slack is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

In normal mode, the PLL will compensate the clocks for the delay of the clock tree.

In other words, the PLL's output clock will be "ahead" of the input clock in such a way that, at the end of the clock tree, the PLL clock will be in phase with the input clock.

derive_pll_clocks

^^ Add this, and TimeQuest will automatically create and constrain all the PLL output clocks