Clock delay is too long...

FPGA's have relatively long, pre-built, clock distribution trees.

Due to that, when you generate a clock using logic, it's going to have a relatively long delay compared to the source clock. Which means using logic generated clocks tends to be a bad practice.

If you can't modify the IP, I suggest you use a PLL to generate two 250 MHz clocks, with different phases. Feed one to the IP block and use the other to receive data from the 125 MHz clock.

By choosing a suitable phase delay between the two 250 MHz clocks, you might be able to work around your problem.