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Occasional Contributor

2 years ago

Solved

Clock constraints for divided clocks

Hi, I am wondering about clock constraints for divided-generated clocks. I made a slow-clock generation block which has counters for divide. It has 3 counters. cnt1 divides 10 MHz clock coun...

Timing

RichardT_altera
2 years ago
You may checkout the forum post here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/how-to-constrain-low-frequency-clocks/m-p/16798/highlight/true?profile.language=ko
It seems for these very low frequencies you just lie. R
Reference:
https://jontio.zapto.org/hda1/fpga_intro/50%20Mbps%20UART%20in%20an%20FPGA%20my%20intro%20into%20FPGA.html
Best Regards,
Richard Tan

RichardT_altera

Super Contributor

2 years ago

You may checkout the forum post here:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/how-to-constrain-low-frequency-clocks/m-p/16798/highlight/true?profile.language=ko

It seems for these very low frequencies you just lie. R
Reference:

https://jontio.zapto.org/hda1/fpga_intro/50%20Mbps%20UART%20in%20an%20FPGA%20my%20intro%20into%20FPGA.html

Best Regards,

Richard Tan

HKana17

Occasional Contributor

2 years ago

Dear Richard,

Thank you for the information.

I check the materials first.

Thank you.

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Clock constraints for divided clocks

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