Forum Discussion
HKana17
Occasional Contributor
Occasional ContributorClock constraints for divided clocks
Hi, I am wondering about clock constraints for divided-generated clocks. I made a slow-clock generation block which has counters for divide. It has 3 counters. cnt1 divides 10 MHz clock coun...
You may checkout the forum post here:
It seems for these very low frequencies you just lie. R
Reference:Best Regards,
Richard Tan
RichardT_altera
Super Contributor
Super ContributorYou may checkout the forum post here:
It seems for these very low frequencies you just lie. R
Reference:
Best Regards,
Richard Tan
HKana17Occasional Contributor
Occasional ContributorDear Richard,
Thank you for the information.
I check the materials first.
Thank you.
