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HKana17's avatar
HKana17
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2 years ago
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Clock constraints for divided clocks

Hi, I am wondering about clock constraints for divided-generated clocks. I made a slow-clock generation block which has counters for divide. It has 3 counters. cnt1 divides 10 MHz clock coun...
Timing
  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Dear Richard,

    Thank you for the information.

    I check the materials first.

    Thank you.

  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you for letting me know the case that was 13 years ago. I didn't imagine the cause was too low clock frequency to be analyzed.

    This time I took the telling a lie to Timing Analyzer method. I reduced the division rate of PLS1r57ms clock to 15. Warnings or errors on SLOWCLKs went away. Thank you again.

    create_generated_clock -name PLS1r57ms -source [get_pins {PLL_inst|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 15 [get_pins {SLOWCLK_1|cnt1|count[13]|q}]

    create_generated_clock -name PLS7r85ms -source [get_pins {SLOWCLK_1|cnt1|count[13]|q}] -divide_by 5 [get_pins {SLOWCLK_1|cnt2|count[2]|q}]

    create_generated_clock -name PLS94r2ms -source [get_pins {SLOWCLK_1|cnt2|count[2]|q}] -divide_by 12 [get_pins {SLOWCLK_1|cnt3|count[3]|q}]