Clock constrains for GPIO IP core of arria 10

Hi, all

fpga : 10ax115N3f45I1sg

quartus : 18.0.0 standard version

Now I'm using GPIO IP core to design using bus lvds. And for this IP, I use half rate design, read and wirte use seperate clocks. IP design likes below:

gpio_ip gpio_ip_inst(

.fr_ck_in ()

.hr_ck_in ()

.dout()

.fr_ck_out()

.hr_ck_out()

.oe()

.din()

.pad_io()

.pad_io_n()

);

fr_ck_in = 2* hr_ck_in; fr_ck_out = 2* hr_ck_out;

din belongs to hr_ck_out domain. like below:

always @ (posedge hr_ck_out, posedge rst)

if(rst)

din <= #1 4'h0;

else

din <= #1 din + 4'h1;

Now for the input, I saw the din as the async input; And for the output, I will not output the source clock. (async output)

fr_ck_out/hr_ck_out; fr_ck_in/hr_ck_in are all from the same PLL

/////output

And for output hr_ddio, I found that for the din (din[0] and din[2]， din[1] and din[3]) generated current rising edge of hr_ck_out, it will output at hr_ddio_dout at the next rising edge and falling edge of hr_ck_out. And from the timing analysis result, there's no timing violation. And I didn't found any timing path from din to hr_ddio_dout and only exist the path from din to dr_ddio_datain*. So I don't think there necessary need to set all output ddio timing constrain, right?

///input

And for input, just because it belongs to async input, there's no necessary need to set the ddio timing constrains and only make sure fr_ck_in and hr_ck_in from the same PLL, right?

////result.

So, for the only constrain for the GPIO design, it only need one constrain: derive_pll_clocks, right?

BRs,

Lambert