Forum Discussion
Occasional ContributorCLK-30028 - Invalid Generated Clock
ContributorQuartus doesn't even support derive_pll_clocks with Stratix 10 and Agilex. Quartus supports derive_pll_clocks for Arria 10, Cyclone 10 GX, and earlier device families. But for some perplexing reason Intel/Altera decided not to support it starting with Stratix 10.
Where derive_pll_clocks is supported, it is certainly the preferred method for constraining PLL output clocks, being the simplest method for the user and the least error prone. It looks at the configuration of each PLL instance and automatically translates that to the correct create_generated_clock constraints. No good reason not to use it, if supported. But for Stratix 10 and Agilex it's not supported, so that's moot.
In the absence of derive_pll_clocks, you do need create_generated_clock constraints for the PLL output clocks.
If you instantiate your IOPLL via wizard-generated IP, then the IP will include the necessary constraints.
If you manually instantiate your IOPLL atom without making use of the wizard-generated IP, then you do need to also manually add the appropriate create_generated_clock constraints. And make sure they're correct for your PLL configuration! Quartus won't necessarily complain if they don't match the PLL configuration, and then your static timing analysis will just be wrong.
sstrellSuper Contributor
derive_pll_clocks is supported with the newer devices, you just don't need to explicitly put it in your .sdc file anymore. The generated clock constraints are automatically created.
- roeekalinsky
@sstrell, that doesn't appear to be the case. Have you tried it? I just tried it again to confirm. Quartus is definitely not automatically creating generated clock constraints for PLL clocks from a hand-instantiated IOPLL atom in Stratix 10 or Agilex. Without user-added create_generated_clock constraints, the PLL clocks remain unconstrained.
This can be confirmed in multiple places:
- During the flow, Quartus rightly issues "Warning (332060): .... <name> was determined to be a clock but was found without an associated clock assignment" for each used PLL clock.
- During the flow, the PLL clocks don't show up in the "Info (332111)" tables that list the constrained clocks found in the design and their periods.
- In the STA report, in the "Clocks" table, the PLL clocks don't show up.
- In the STA report, in the "Unconstrained Paths Summary" table, you can see them counted in the "Unconstrained Clocks" count.
- In the STA report, in the "Clock Status Summary" table, they explicitly show up with Status "Unconstrained" .
- In the STA report, paths in these clock domains aren't analyzed.
- Etc.
- sstrell
I've never not used the IP Parameter Editor for a PLL, so I don't doubt you.
OrFI've used Wizard-Generated IP ! , and I do have the sdc for the pll !.
I do see the ip.sdc in the sdc files list .
I will check if I can upload the archive project and post it here .
- OrF
I have the test case Archive, but it is 31M byte.
Maximum upload to here is 24Mbyte - is there any other place I can upload the test case ?
