Honored ContributorHello,
I have two clock domains in my design 1. variable clock ~64Mhz (driven from external pll) 2. 100mhz stable clock. Does anybody have an idea how to check clock 64M existent ( without attaching it to a pll) ?? sampling 64M with 100Mhz will creat a metastability. thanks
Honored ContributorYes it will create a metastability, that you can control by using several registers in cascade, all clocked at 100MHz. 3 stages should be enough. Just Google a bit for "clock domain crossing".
Honored ContributorThis is what I did, I sampled ~64Mhz clock with the stable 100Mhz. 3 samples.
I made a shift register with 5 stages. after that I compared the 5bit vector to "11111" or "00000" . if its true it means there is no toggling in 64Mhz. Many thanks
